This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2001-159944, filed on May 29, 2001; the entire contents of which are incorporated herein by reference.
1. Field of the Invention
The present invention relates to a semiconductor memory device.
2. Description of Related Art
Generally, one of the effective methods of reducing the power consumption of a semiconductor integrated circuit including MOSFET""s, particularly the power consumption of a CMOS integrated circuit, is to decrease a driving voltage. If the driving voltage is decreased, however, the operating speed of the CMOS circuit is reduced. If not only the driving voltage but also a threshold voltage is decreased, it is possible to reduce the power consumption of the circuit in operation without reducing the operating speed thereof. If the threshold is decreased, however, the sub-threshold current of each MOSFET increases and the power consumption of the circuit in a standby state thereby increases. Particularly, in a semiconductor memory device, if the driving voltage thereof is to be decreased, such disadvantages as the decrease of a gain in an operating range of a CMOS device which constitutes a memory cell, the increase of a stand-by current following the decrease of the threshold Vth of each MOSFET occur. To avoid these disadvantages, there is proposed the use of DTMOS""s (Dynamic Threshold voltage MOSFET""s) each having a gate connected to a substrate, as MOSFET""s which constitute a memory cell. If the DTMOS""s are used, it is possible to decrease a stand-by current and to obtain a large gain at a low driving voltage. It is, therefore, possible to configure a circuit which can stably operate at high speed.
The configuration and layout of a conventional memory cell which uses CMOS devices as constituent elements are shown in FIGS. 8 and 9, respectively. The configuration and layout of a conventional memory cell which uses DTMOS""s as constituent elements are shown in FIGS. 10 and 11, respectively.
In FIG. 8, a memory cell 70 includes two transfer gates 72 and 73, and a data storage section 80. The data storage section 80 includes a CMOS inverter 83 which consists of a p channel MOSFET 81 and an n channel MOSFET 82, and a CMOS inverter 86 which consists of a p channel MOSFET 84 and an n channel MOSFET 85. The input terminal of the CMOS inverter 83 is connected to the output terminal of the CMOS inverter 86. The output terminal of the CMOS inverter 83 is connected to the input terminal of the CMOS inverter 86. Therefore, the CMOS inverters 83 and 86 constitute a cross-connection configuration. Each of the transfer gates 72 and 73 consists of an n channel MOSFET and the gate thereof is connected to a word line WL.
In addition, the drain of the transfer gate 72 is connected to a bit line BL and the source thereof is connected to the output terminal of the CMOS inverter 83, i.e., the drains of the MOSFET""s 81 and 82. The drain of the transfer gate 73 is connected to a bit line/BL and the source thereof is connected to the output terminal of the CMOS inverter 86, i.e., the drains of the MOSFET""s 84 and 85. Further, a well or a substrate in which the transfer gates 72 and 73 are formed is connected to the sources of the MOSFET""s 82 and 85.
In the memory cell 70 constituted as stated above, the transfer gates 72 and 73 and the n channel MOSFET""s 82 and 85 are formed in the same well 101 and the p channel MOSFET""s 81 and 84 are formed in the same well 102 as shown in FIG. 9. The gates of the transfer gates 72 and 73 are configured as the word line WL of, for example, polysilicon. A diffused layer 72b which becomes the drain of the transfer gate 72 is connected to the bit line BL and a diffused layer 72a which becomes the source of the transfer gate 72, becomes the drain of the MOSFET 82. A diffused layer 73b which becomes the drain of the transfer gate 73 is connected to the bit line/BL and a diffused layer 73a which becomes the source of the transfer gate 73, becomes the drain of the MOSFET 85. Diffused layers 82a and 85a which become the sources of the MOSFET""s 82 and 85 are connected to the well 101 and a ground power supply by wirings, respectively.
Further, the gates of the MOSFET""s 81 and 82 are configured as a wiring 105 of, for example, polysilicon. This wiring 105 is connected to diffused layers 84b and 73a which become the drains of the MOSFET""s 84 and 85, respectively. The gates of the MOSFET""s 84 and 85 are constituted as a wiring 106 made of, for example, polysilicon. This wiring 106 is connected to diffused layers 81b and 72a which become the drains of the MOSFET""s 81 and 82, respectively. Diffused layers 81a and 84a which become the sources of the MOSFET""s 81 and 84, respectively, are connected to the well 102 and a driving power supply.
Meanwhile, as shown in FIG. 10, the conventional memory cell which uses DTMOS""s includes two transfer gates 76 and 77, and a data storage section 90. The data storage section 90 includes a CMOS inverter 93 which consists of a p channel MOSFET 91 and an n channel MOSFET 92, and a CMOS inverter 96 which consists of a p channel MOSFET 94 and an n channel MOSFET 95. The input terminal of the CMOS inverter 93 is connected to the output terminal of the CMOS inverter 96. The output terminal of the CMOS inverter 93 is connected to the input terminal of the CMOS inverter 96. In addition, the potential of the input terminal of the CMOS inverter 93 is applied as the substrate bias of the CMOS inverter 93. The potential of the input terminal of the CMOS inverter 96 is applied as the substrate bias of the CMOS inverter 96.
Each of the transfer gates 76 and 77 consists of an n channel MOSFET and the gate thereof is connected to a word line WL. The drain of the transfer gate 76 is connected to a bit line BL, and the source thereof is connected to the output terminal of the CMOS inverter 93, i.e., the drains of the MOSFET""s 91 and 92. The drain of the transfer gate 77 is connected to a bit line/BL, and the source thereof is connected to the output terminal of the CMOS inverter 96, i.e., the drains of the MOSFET""s 94 and 95. A well or a substrate in which the transfer gate 76 is formed is connected to the gate of the transfer gate 76 or the substrate. A well or a substrate in which the transfer gate 77 is formed is connected to the gate of the transfer gate 77 or the substrate.
In the memory cell 90 constituted as stated above, as shown in FIG. 11, the transfer gates 76 and 77, the n channel MOSFET""s 92 and 95, and the p channel MOSFET""s 91 and 94 are formed in different wells. Namely, the transfer gate 76 is formed in a well 111, the transfer gate 77 is formed in a well 112, the MOSFET 92 is formed in a well 113, the MOSFET 95 is formed in a well 114, the MOSFET 91 is formed in a well 115, and the MOSFET 94 is formed in a well 116.
The gates of the transfer gates 76 and 77 are configured as a word line WL of, for example, polysilicon. In addition, a diffused layer 76b which becomes the drain of the transfer gate 76, is connected to the bit line BL. A diffused layer 76a which becomes the source of the transfer gate 76 is connected to diffused layers 91b and 92b which become the drains of the MOSFET""s 91 and 92, respectively, and also connected to a wiring 122 of, for example, polysilicon which becomes the gates of the MOSFET""s 94 and 95. A diffused layer 77b which becomes the drain of the transfer gate 77 is connected to a bit line/BL. A diffused layer 77a which becomes the source of the transfer gate 77 is connected to diffused layers 94b and 95b which become the drains of the MOSFET""s 94 and 95, respectively and also connected to a wiring 121 of, for example, polysilicon which becomes the gates of the MOSFET""s 91 and 92. Diffused layers 92a and 95a which become the sources of the MOSFET""s 92 and 95 are connected to a ground power supply by wirings, respectively. Diffused layers 91a and 94a which become the sources of the MOSFET""s 91 and 94 are connected to a driving power supply by wirings, respectively.
The word line WL which becomes the gates of the transfer gates 76 and 77 contacts with the wells 111 and 112. The wiring 121 which becomes the gates of the MOSFET""s 91 and 92 contacts with the wells 113 and 115. The wiring 122 which becomes the gates of the MOSFET""s 94 and 95 contacts with the wells 114 and 116.
As can be seen, the conventional memory cell which employs DTMOS""s as constituent elements is required to form the wells of respective transistors independently of one another in light of a substrate bias, thereby disadvantageously increasing the area of the memory cell compared with the memory cell which employs CMOS devices as constituent elements.
Further, in the memory cell which consists of two inverters and two transfer gates, one of the two bit lines always becomes H level and the other bit line always becomes L level when data is read from the cell. If a current is not applied to the transfer gate on the H level side, the potential difference between the bit lines has sharp change and high speed operation can be performed. However, in the conventional memory cell which employs DTMOS""s, the two transfer gates are simultaneously opened and closed and equal in operating characteristic, making it disadvantageously impossible to perform high speed operation.
A semiconductor memory device according to a first aspect of the present invention comprises a plurality of memory cells each comprising: a data storage section storing data; and a transfer gate section having a MOSFET of a first conductive type for writing the data to the data storage section and reading the data from the data storage section, and wherein a potential corresponding to the data stored in the data storage section is applied as a substrate bias of the MOSFET.
A semiconductor memory device according to a second aspect of the present invention comprises a plurality of memory cells each comprising: first to fourth wells formed on a semiconductor substrate and isolated from one another; a first MOSFET of a first conductive type formed in the first well, having a diffused layer becoming a drain and connected to one of a pair of bit lines, and having a gate connected to a word line; a second MOSFET of the first conductive type formed in the first well, having a diffused layer becoming a drain, the diffused layer being a common diffused layer becoming a source of the first MOSFET; a third MOSFET of the first conductive type formed in the second well, having a diffused layer becoming a drain and connected to the other bit line of the pair of bit lines, and having a gate connected to the word line; a fourth MOSFET of the first conductive type formed in the second well, having a diffused layer becoming a drain, the diffused layer being a common diffused layer becoming a source of the third MOSFET; a fifth MOSFET of a second conductive type formed in the third well, and having a gate common to the fifth MOSFET and the second MOSFET; a sixth MOSFET of the second conductive type formed in the fourth well, and having a gate common to the sixth MOSFET and the fourth MOSFET; a first wiring connecting a diffused layer becoming a source of the second MOSFET to a diffused layer becoming the drain of the fifth MOSFET; a second wiring connecting a diffused layer becoming a source of the fourth MOSFET to a diffused layer becoming a drain of the sixth MOSFET; a first contact section formed in an isolation region isolating the first well from the third well, and connecting the first wiring to the gates of the fourth and sixth MOSFET""s; and a second contact section formed in an isolation region isolating the second well from the fourth well, and connecting the second wiring to the gates of the second and fifth MOSFET, and wherein the first well is connected to the third well through the gates of the second and fifth MOSFET""s, and the second well is connected to the fourth well through the gates of the fourth and sixth MOSFET""s.